The present invention relates generally to self time memories, and more specifically, to methods for controlling the number of core cells placed in the self time column of a memory for controlling bit line separation in a memory during memory read access and the like.
In self time memories, the circuitry used to control bit line separation has typically consisted of a single bank of core cells tied to a common self time word line. The self time bit line tracks to the memory array bit line by matching its capacitance and driving the self time bit line with multiple core cells such that the self time bit line separation or slew rate is a fixed multiple of the array bit line. The self time bit line drives into a simple inverter sense amp which then triggers the internal clock low and enables the memory array sense amps. The number of memory core cells used to drive the self time bit line can be adjusted to give a desired signal development (Vbl), as shown in FIG. 1. Thus, the bit line separation is an inverse function of the number of self time core cells connected to the self time word line (STWL), or xe2x80x9cM-factorxe2x80x9d of the memory. For instance, FIG. 2 illustrates a self time circuit 100 wherein the self time word line xe2x80x9cSTWLxe2x80x9d 102 of the circuit 100 is connected to eight core cells 104. Thus, the circuit 100 illustrated would provide an M-factor of eight (8).
To modify the bit line separation, for example, to tune in a value of bit line separation that is sufficiently fast to accommodate the margin speed of the memory, the M-factor (i.e., number of core cells connected to the self-time word line) must be changed by either connecting or disconnecting core cells from the self time word line. Thus, as shown in FIG. 1, modification of the bit line separation by increasing the M-factor from eight (8) to nine (9) for the circuit 100 shown, requires that an additional core cell 106 be connected. Presently, memories are provided with a fixed core cell multiple based on simulated results during memory development. However, connection or disconnection of core cells requires multiple mask changes making failure analysis or experimentation difficult and costly.
Consequently, it is desirable to more readily change the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by respectively increasing or decreasing internal margins of the memory (bit line separation).
Accordingly, the present invention changes the internal timing of a memory by means of a compiler code to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively.
In accordance with one aspect of the invention, a method is provided for controlling bit line separation of the memory by controlling the number of core cells used for driving a self time column of the memory. In one embodiment, the method includes the steps of selecting a variable within a compiler compiling the memory for varying the number of core cells used for driving the self time column of the memory, and tiling core cells of the memory according to the received variable during compilation of the memory so as to configure the self time column to have a number of core cells suitable for providing a desired self time bit line separation. In embodiments of the invention, the variable is hard coded within the compiler or entered into the compiler by a user.
In a second aspect of the invention, a self time circuit for a memory is provided. In exemplary embodiments, the self time circuit comprises a plurality of core cells within the memory and a plurality of self time word lines, each of the self time lines being coupled to at least one core cell for activating the core cell. In accordance with the present invention, the number of core cells coupled to at least one of the self time word lines is set during compilation by a compiler by adjusting a variable of the compiler for controlling bit line separation of the memory when the memory is accessed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.